The joining together of semiconductor substrates to metallic substrates has been practiced in the micro-fabrication technology domain for several decades, and more recently, in the nano-fabrication domain. But it has always involved the use of an intermediate layer of a solder, adhesive, epoxy, glass frit, or other joining material or compound between the two substrates to provide sufficient adhesive strength for practical applications. Metal and semiconductor substrates have been joined together for one or more purposes. First, it can provide increased mechanical stiffness and strength to a fragile semiconductor substrate, thereby making the semiconductor less susceptible to breakage during normal handling, as well as during subsequent fabrication and packaging processes. Second, it can provide electrical connection(s) to a semiconductor substrate by which current and/or voltage can be applied to operate the device(s). Third, it can provide the ability to move heat away from the semiconductor device where the metal substrate functions as a thermal heat sink or thermal heat spreader to the semiconductor device, thereby enabling the temperature of the semiconductor device to be better regulated or maintained at acceptable levels during operation. Fourth, it can provide electromagnetic shielding of devices made in the semiconductor substrate, to thereby reduce interference from nearby Alternating Current (AC), Radio Frequency (RF) and microwave (mm-wave) sources, by enclosing, either partially or entirely, the semiconductor devices by conductive metal materials. Fifth, it can facilitate the packaging of the semiconductor device(s). In most cases, the package for semiconductors is made from a metal, plastic or ceramic material or some combination of material types and the semiconductor substrate is mated to the die attachment area in the package where a metal material may be located. This metal can be a fundamental portion of the package housing or it may be a thin- or thick-film of metal deposited and suitably patterned within the package. In nearly all circumstances, the attachment of the semiconductor substrate to the package is performed using either a solder or a gluing agent such as epoxy.
Despite the reasons and merits of joining a semiconductor substrate to a metallic substrate for many applications, it is understood and recognized that the use of an intermediate layer or layers between a metal substrate and a semiconductor substrate to mate the two substrates to one another has many disadvantages and shortcomings.
Intermediate layers, such as solders, epoxies, glass frits, adhesives and the like, that are commonly used for joining a semiconductor and metal substrate together can result in large “built-in” residual stresses that can have detrimental effects on semiconductor device performance. For example, if a soldering material is used to mate a semiconductor to a metal substrate, the temperature of the mating process must be performed at approximately the melting or alloying temperature of the soldering material, which is typically well over one-hundred degrees Celsius. Metals usually have relatively large coefficients of thermal expansion whereas semiconductors have comparatively lower coefficients of thermal expansion, and therefore the differing thermal expansion coefficients of the materials in this system combined with the elevated temperatures required to perform the soldering process can result in large built-in stresses between the mated substrates once they are cooled to room temperature.
Built-in stresses frequently result in many negative consequences for the performance of semiconductor device(s). For example, it is well known that most semiconductors can have their bandgaps and energy levels modified by the application of mechanical strains on the substrate material due to the piezoresistive effect in semiconductors. Consequently, if the mating process results in built-in stresses, these built-in stresses can cause the bandgaps and energy states in the semiconductor material to be altered, thereby modifying the device behavior such as changing the threshold voltages in transistors or shifting the wavelength of the radiation for solid-state light emitting devices.
Large built-in stresses have also been known to appreciably lower the reliability of semiconductor devices. For example, semiconductor devices frequently heat-up due to the power dissipated during operation, thereby resulting in large thermal stresses developing between the mated materials. This thermal stress can be due to the differing thermal expansion coefficients of the materials used in these systems in which metals typically have larger coefficients of thermal expansion than semiconductors. Under some circumstances, this thermal stress can become sufficiently large so as to result in the fracture of the semiconductor substrate, thereby resulting in an inoperable semiconductor device(s). Additionally, a sufficiently large thermal stress between a joined semiconductor and metal substrate can result in the substrates breaking apart due to a failure at the interface. Moreover, even if the thermal stress is not sufficient large to cause fracture in one operational cycle, fracture can still result after many operational cycles (e.g., power on for some period of time with a resultant increase in heating and thermal stress, followed by a period of time with the power off and a decrease in heating and thermal stress, followed by a period of time with power on again with a resultant increase in heating and thermal stress, etc.), due to fatigue effects in the semiconductor substrate over several repeated cycles of operation.
Additionally, the solders used to join metals to semiconductors can re-flow from the interface to other areas of the device and/or package, which can result in a number of problems, such as the electrical shorting of the device. For example, semiconductor devices typically heat up during operation and this elevated temperature, possibly combined with the stresses that the solder is exposed to (due to the different coefficients of thermal expansion of the materials used in the system) and the favorable wetting properties of the solder on the semiconductor and metal substrates, can cause the solder to partly or completely melt and re-flow to other areas of the device or package, or both. In some instances, this solder may re-flow to locations that cause an electrical shorting between parts of the device meant to be electronically isolated, thereby resulting in catastrophic failure of the device.
Alternatively, or in addition to these phenomena, the intermediate layer(s) used for joining metals to semiconductors under operational conditions can re-flow away from the areas where electrical current is flowing or a voltage potential is applied, thereby resulting in an open circuit condition as well as other serious and negative effects on the semiconductor device(s).
Similarly, if the solder re-flows from the interface between the metal and semiconductor substrates, the result will be an increase in the thermal resistance at the location where the solder is no longer present. As a result, the semiconductor's temperature will rise, since the heat cannot be transferred away from the semiconductor as effectively when the solder is present. Thereupon, the interface temperature will continue to rise, thereby causing more solder to re-flow, and so on. Consequently, a positive feedback process loop is established in which the semiconductor heating reinforces the solder migration, which causes an additional temperature rise in the semiconductor, and so on, with the eventuality that the semiconductor fails to operate.
For some semiconductor devices, even for relatively small temperature increases (e.g., a few degrees Celsius), there can be a very large decrease in device reliability. Therefore, any phenomena resulting in a slight over-temperature of the semiconductor devices can have significant and negative effects on the semiconductor device reliability.
Additionally, the soldering processes typically use a flux material to facilitate the soldering. Flux material mixtures are highly corrosive, and as a by-product of the soldering process, some residual flux will be left remaining on the surfaces after the joining process has been completed, and can therefore have a negative effect on the semiconductor device and/or the metal substrate.
The use of epoxies and other gluing agents also has many disadvantages for the mating of semiconductor devices to metal substrates. Most epoxies and glues are in a liquefied form to facilitate the dispensing of these agents onto the substrates to be mated. Subsequently, after spreading the epoxy or glues onto the surfaces to be joined and physically contacting them, the epoxy or glues are then “cured” whereby the solvents used to liquefy the epoxy or glues are evaporated or driven off, and/or the components within the mixture react so that the epoxy or glue hardens or stiffens. However, during this curing or reacting process, the epoxy or glue undergoes a considerable amount of shrinkage, whereby a large amount of residual stress between the semiconductor and metal substrates results. This residual stress will have similar negative consequences on the semiconductor performance and reliability as a result of the soldering process described above.
Additionally, epoxies and glues typically will display mechanical creep over time. Creep is the plastic deformation of a material that is subjected to a stress below its yield stress and is accelerated at higher temperatures. This creep phenomenon has many deleterious effects such as a constantly changing stress loading on the semiconductor material and device thereby making any schemes employed to reduce, mitigate, and/or compensate these stresses difficult or impossible.
Additionally, the solvents and other components used in the epoxies and glue mixtures will continue to “outgas” from the epoxy or gluing materials for many years into the future even after a thorough “curing” process of these materials. These outgassed substances can have a deleterious effect, such as contamination or corrosion, of the semiconductor device(s).
Consequently, this is an enormous opportunity for a new technique by which a metal substrate can be directly bonded to a semiconductor substrate without an intermediate layer. There is also an enormous opportunity for a new technique in which a metal substrate can be directly bonded to a semiconductor substrate at low temperatures without an intermediate layer.
Direct wafer bonding has been a widely used fabrication technique in the Integrated Circuit (IC) and Micro-Electro-Mechanical Systems (MEMS) technology areas for several years. This technique has been primarily used to bond two silicon wafers together using no adhesives or intermediate layers. Frequently, one of the silicon wafers is oxidized prior to the bonding. On occasion, different types of semiconductors have been direct wafer bonded together as well.
The direct wafer bonding process of semiconductor wafers usually involves a sequence of steps, including cleaning of the wafers, preparation of the wafer surfaces, physical contact of the wafers together, and then followed by a high temperature anneal. The elevated temperature anneal is necessary to increase the bond strength and is typically performed at temperatures at or above 800 degrees Celsius, with temperature at or above 1000 degrees Celsius being the most common.
The high temperatures of the anneal required for direct wafer bonding are problematic for many substrate materials as well as for substrates having electronic, photonic, or MEMS devices made in the semiconductor material since the high annealing temperatures result in a severe degradation of device performance and possibly the complete inability of the device to function. Therefore, any semiconductor-to-semiconductor wafer bonding employed in fabrication of devices is usually performed before any active devices have been implemented in the semiconductor substrates.
Nevertheless, in many applications it is desirable to bond a metal substrate to a semiconductor substrate without the use of an intermediate layer. Furthermore, in some applications is it is not only desirable to bond a metal substrate to a semiconductor substrate without the use of an intermediate layer, but to do so while also obtaining a low electrical resistance pathway from the metal substrate to the semiconductor, as well in the opposite current direction from the semiconductor to the metal substrate. Moreover, in some further applications, it is not only desirable to bond a metal substrate to a semiconductor substrate without the use of an intermediate layer, but to do so while also obtaining a low thermal resistance between the metal substrate and the semiconductor substrate. It is also desirable to perform bonding between a semiconductor substrate and a metal substrate at low-temperatures.